This invention generally relates to diffusion barrier layers and more particularly to selectively deposited metal diffusion barrier layers.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low RC (resistance capacitance) metal interconnect properties, particularly wherein submicron via/contact holes (inter-layer interconnects) and intra-layer interconnects have increasingly high aspect ratios.
In the fabrication of semiconductor devices, increased device density requires multiple layers, making necessary the provision a multi-layered interconnect structure. Such a multi-layered interconnect structure typically includes intra-layer conductive interconnects (wiring) and inter-layer conductive interconnects formed by openings or holes in an insulating layer (inter-metal dielectric layer). Such holes are commonly referred to as contact holes, i.e., when the hole extends through an insulating layer to an active device area, or vias, i.e., when the hole extends through an insulating layer between two conductive layers. The interface of the metal-metal contact is important since a poor contact will result in higher resistance thereby increasing signal transport times.
In a typical process for forming multiple layer interconnect structure, such as for example, a damascene process, an insulating inter-metal dielectric (IMD) layer is deposited on a conductive layer, an opening is then formed through the IMD by conventional photolithographic and etching techniques, followed by filling the opening with a conductive material, such as tungsten, aluminum or copper. Excess conductive material remaining on the surface of the IMD layer is typically removed by chemical-mechanical polishing (CMP). One such method is known as a dual damascene technique includes the formation of a via hole in communication with an upper trench section, both such openings subsequently simultaneously filled with a conductive material, such as a metal, to form a conductive inter-layer electrical contact with an intra-layer conductive line.
Signal transport speed is of great concern in the semiconductor processing art for obvious performance reasons. The signal transport speed of semiconductor circuitry varies inversely with the resistance and capacitance (RC) of the interconnections. As integrated circuits become more complex and feature sizes decrease, the effect of an RC delay becomes greater.
One way to increase the signal speed of semiconductor circuitry is to reduce the resistance of a conductive interconnects. Aluminum (Al) has been conventionally used for forming conductive interconnects because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the submicron range, step coverage problems have arisen with the use of Al, decreasing the reliability of interconnections formed between different wiring layers. Decreased step coverage results in high current density and enhanced electromigration.
One approach to improving metal interconnections has included completely filling via holes with plugs of a metal, such as tungsten (W). Many current semiconductor devices use Al for intra-layer interconnects and W plugs for inter-layer interconnections at different levels. However, the use of W has several disadvantages. For example, most W processes are complex and expensive and W has a relatively high resistivity. Consequently, Joule heating of W under high current conditions may enhance electromigration of adjacent Al wiring. Furthermore, W plugs are susceptible to void formation, resulting in poor interface contact and a corresponding high contact resistance at metal interfaces.
Copper (Cu) and copper alloys have been favorably considered for replacing Al and W in VLSI interconnect metallizations. Cu has a lower resistivity than Al, making Cu attractive for intra-layer interconnection wiring. In addition, Cu has improved electrical properties compared to W, making Cu additionally attractive for use as a conductive plug for inter-layer interconnections.
There, however, some disadvantages with the use of Cu or Cu alloys. For example, Cu readily diffuses through silicon dioxide, a typical inter-metal dielectric (IMD) material, and into silicon elements, adversely affecting the electrical properties thereof. For example, Cu is a deep-level dopant in silicon which acts to lower the semiconductor minority lifetime and increases junction leakage current. One solution to this problem has been to form diffusion barrier layers to prevent Cu diffusion. While thicker diffusion barriers may be required, for example, on via sidewalls thereby preventing Cu diffusion into the IMD layer, thinner barrier layers may be preferable at the bottom of the via hole which includes a metallic underlayer, where low resistance between metal contacts is increasingly important. One consideration is that, as barrier thickness decreases below 1 micron, physical vapor deposition (PVD) methods cannot be used due to poor step coverage, making chemical vapor deposition (CVD) the method of choice.
There is therefore a need in the semiconductor processing art to develop a CVD process whereby effective barrier layers may be deposited at varying thickness to maximize their effectiveness, for example, by deposition of a thicker layer on a via sidewall compared to, for example, the via hole bottom which includes a metallic underlayer.
It is therefore an object of the invention to provide a method for depositing diffusion barrier films in semiconductor manufacturing processes whereby relatively thinner diffusion barrier films are selectively deposited in areas between metal-metal contacts while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for selectively depositing a metal diffusion barrier layer in a semiconductor structure to reduce an electrical contact resistance with respect to an underlying copper layer while maintaining a copper diffusion resistance along the semiconductor feature sidewalls.
In a first embodiment according to the present invention, the method includes providing at least one anisotropically etched opening extending through at least one insulating layer and in closed communication with a copper underlayer; depositing a metal nitride layer over the at least one anisotropically etched opening under conditions according to a CVD process such that the metal nitride layer has a relatively higher deposition rate onto sidewalls of the at least one anisotropically etched opening for a period of time compared to a deposition rate over the copper underlayer to form; and, exposing the metal nitride layer to a silicon containing gaseous ambient under conditions such that silicon is incorporated into the metal nitride layer to form a silicided metal nitride layer having a thickness over the copper underlayer thinner by about 10 Angstroms to 60 Angstroms compared to a sidewall thickness.
These and other embodiments, aspects and features of the invention will become better understood from a detailed description of the preferred embodiments of the invention which are described in conjunction with the accompanying drawings.